We looked at the new AMD Ryzen 7 1700 processor, a tough competitor to Intel's processors, albeit with some minor gaming performance issues.

[nextpage title=”INTRODUCTION” ]

INTRODUCTION

After a long journey through the desert, AMD has finally launched AMD Ryzen, processors that are based on the new Zen architecture, to the market. These new processors come to end with a series of processors, which have worked quite well, with prices competitive, but did not support DDR4 and to compete with Intel. AMD Ryzen wants to end the golden months of Intel, where it has put the price it wanted, because it had no direct competition in the processor market.

AMD Ryzen will be divided into three families. The high-end range would be formed by the AMD Ryzen 7, the advanced range would be formed by the AMD Ryzen 5 and the mid-range by the AMD Ryzen 3, while the entry and discrete range would remain for the APUs and other discrete solutions that AMD It will be launched in the near future, according to reports, during the second half of this year.

The AMD Ryzen promise to end the tyranny of Intel in the market, with very high prices, as we well know. The idea of ​​AMD Ryzen is to compete in performance, being similar or superior to that of Intel processors in depending on what cases and above all, in price. AMD prices are very competitive and in some cases, such as the AMD Ryzen 7 1700, which costs around € 370, a processor that according to AMD should compete directly with the Intel i7 7700K processor, from the Kaby Lake family and that we analyzed some time ago.

Thanks to Coolmod for having given us this processor for analysis and to Gigabyte for giving us the motherboard for the benchmarks.

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[nextpage title=”ZEN” ]

ZEN ARCHITECTURE

The first thing we have to know about this architecture, or rather see, is the diagram of what the processor will be internally. We can see that the core is divided into the front-end in blue and the rest of the core becomes the back-end. The front-end is where instructions arrive at the kernel, prediction branches are activated, and instructions are decoded into micro-operations before being placed in a micro-operations queue. We can see in red the part of the back-en that deals with instructions based on Integer (INT), such as integer mathematics, loops, loads and storage. In orange we can see the Floating Point (FP) part of the back-end, which is focused on different forms of mathematical calculations. INT and FP segments have their own execution port schedulers, which act separately.

It looks a bit similar to other high-performance processor cores and it is. Apparently there is a high-level way of 'doing things', when we talk about x86, with three levels of cache, TLB at various levels, a set of decoders that dispatch a combination 4-5 + in micro-processes per cycle, a very large 150+ micro-operations queue, resources to withdraw shared resources, AVX support and, how could it be otherwise, Simultaneous Hyper-Trheading.

major developments

First and foremost, is the inclusion of the micro-operations cache. This allows the instructions to be used to be called in the micro-operations queue instead of being decoded again, thus avoiding a repetitive process. Micro-operation caches are typically relatively small. Intel version can support 1536 micro-operations by eight-way association. The Micro-Operations Cache for Zen supports up to 2048 micro-operations with up to eight operations per cache line.

The structure of the cache is the second important point. Zen makes use of a 1Kb L64 cache per core with four-way associativity, with a 1Kb L32 cache of data per core with eight-way associativity. Size and accessibility determine how often a cache line is lost and is typically a trade-off for area and power (the larger the cache, the more area required and that requires more power) . The instruction cache, per cycle, can support a 32-byte search while the data cache allows two 16-byte payloads and one 16-byte memory per cycle.

Regarding the L2 cache, it has a capacity of 512Kb with eight paths for each core. This cache is twice the size of the Skylake's L2 cache, which is 256Kb and four-way, while Broadwell's is 256Kb and eight-way. Typically doubling the cache size gives 1414 the chance of a cache hit, reducing the need to go further to find data, but comes at the expense of die area. This should have a big impact on performance metrics and AMD is promoting faster cache-to-cache transfers than previous generations. Both L1 and L2 caches are write caches, enhancing Bulldozer's L1 write cache.

Finally we have the L3 cache, which is 8MB and 2 lanes, of which we know that it is distributed in a module with four cores, providing 3MB of L16 cache per core or 3MB of L8 cache for each of the eight cores of the Zen processors. Both caches are separate, therefore there are two XNUMXMB modules, so it acts as a top-level cache for every four cores.

AMD processors have SMT or Simulteneous Multi-Threading technology. This technology is very similar to Intel technology, in fact, in a broad way, so to speak, both technologies are the same, but they have slight differences. The SMT has the ability to drive performance gains by allowing a second thread, on the same core, to access multiple execution ports, work queues, and caches. The SMT also requires hardware level support. Not all structures can be shared directly between threads and can be algorithmically partitioned, statically partitioned or used in alternating cycles.

These processors also have dual schedulers, one for INT and one for FP, which is different from Intel's joint scheduler / buffer implementation.

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[nextpage title=”DIE” ]

AMD Ryzen Die

AMD prior to launching Ryzen, committed to achieving a more than 40% improvement in IPC over Excavator. This depends on a significant improvement in performance, with an equivalent energy consumption per cycle, which would increase efficiency by 40%. According to AMD's announcement at Tech Day, it has achieved a performance improvement of 270% (x2.7), per Watt.

Part of the benefits come from moving from the 28nm TSN process to the 14nm FinFET process of the Global Foundries company, developed thanks to a license acquired from Samsung. The node and the improvements have been documented in an image, which we have left below. AMD claims that Zen is much more than this, with a direct improvement towards immediate performance and not just aimed at efficiency. Zen is built on high-performance x86 fabric cores, which are designed to scale from notebooks to supercomputing systems.

You can see an image on the presentation of the processors, which show the CPU Complex system, called CCX, which shows us the design of a Zen core, structured as a four-processor cluster with the cache. We see how the L2 / L3 cache is structured, confirming that the L2 cache has 2MB per core and the L3 cache has 8MB per CCX module. The picture shows that the L3 cache has a higher inclusion than the L2 cache, which comes from the L3 cache as a victim cache of the L2 data. AMD has indicated that the protocols involved in the design of the L3 cache allow each core to have access to the L3 of each of the cores, depending on the latencies.

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[nextpage title=”FETCH & DECODE” ]

FETCH & DECODE

Fetch

Zen architecture incorporates a branch decoupling system by decoupling. This what allows is the support to speculate on the incoming instruction points to fill the queue, as well as looking for direct and indirect targets. The Branch Target Buffer (BTB), for Zen is described as 'big', but still without concrete numbers, however there is a hierarchical provision for L1 / L2 cache for the BTB. As a corporation, we can highlight that Bulldozer had a L1 BTB cache with 512 inputs and four channels with a single cycle latency and a L2 BTB cache with 5120 inputs and five channels with an additional latency.

The decoupled predictor also enables you to pre-search instructions and fill queues based on internal algorithms, based on previous tasks. Going too far for a specific branch and having it failing at any given time will end up penalizing power, but successful processes should help performance and improve latency through memory parallelism.

We turn to the Translation Lookaside Buffer (TLB), in the predictions of the branches, it looks for recent virtual memory translations of physical addresses to reduce load latency and operate on three levels:

• L0 with 8 entries of any paging size.
• L1 with 64 entries of any paging size.
• L2 with 512 inputs, but with support for 4K and 256K paging only.

Decode

The instruction cache will then send the data through the decoder, which can decode up to four instructions per cycle. As mentioned above, the decoder can merge the operations together in a fast path, such that a single micro-operation goes to the micro-operations queue, but they still represent two instructions, but these will be divided to act on the two managers. This allows the system to fit more closely into the micro-operations queue and allows for higher throughput when possible.

The new Stack Engine comes into play between queuing and forwarding, allowing low-power address generation when already known from previous cycles. This allows the system to save energy, avoiding going through AGU again and having to go through the cache again. The dispatcher can apply six instructions per cycle, with a maximum speed of six instructions per INT programming cycle and up to four FP programming cycles. The sending unit can simultaneously send INT and FP instructions in the same cycle, which maximizes performance.

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[next page title=”SMT” ]

SIMULTANEOUS MULTITHREADING

Zen will be the first AMD architecture to fully introduce a simultaneous multi-threaded structure, and certain parts of the processor will act differently depending on your application. There are many ways to manage the threads, especially to avoid posts where one thread is blocking another that ends in the system hanging. Drivers that communicate with the operating system also have to ensure that they can distinguish between threads running on new cores or when a kernel is already busy.

There are different ways of managing tasks per thread. The basic way is time division, giving each thread an equal part of the pie. This is not always the best policy, especially when you have a dominant performance thread or a thread that creates a large number of stalls or a thread where latency is of paramount importance. In some methodologies the importance of each thread can be marked or determined, although for some of the structures, it is necessary to return to a basic model.

With each thread, AMD performs an internal analysis of the data stream for each one to see which of them have an algorithmic priority. This means that certain threads will require more resources or when the branch should be prioritized to avoid delays to avoid latencies. The elements in blue operate in this methodology.

A thread can also be tagged with a higher priority. This is important for latency-sensitive operations such as touch screen input or user input items that require immediate priority. Address translation buffers work this way, with recent searches giving priority to scratch address translations. The upload queue is similarly enabled, this way, as is normal for low latency workloads, data is required as soon as possible, so the upload queue is perfect for this.

Certain parts of the kernel are statically partitioned, giving each thread equal time. This is mostly done for anything that is normally processed in order, such as anything that comes out of the micro-operations queue, the output queue, and the storage queue. However, when running in SMT mode with a single thread, statically split parts of the core can end up in a bottleneck, as they are idle half the time. The rest of the core is done through competitor scheduling, which means that if a thread demands more resources, it will try to prioritize it if there is room to do it every cycle.

New instructions

Some of the new commands are related to what Intel already uses, such as the case of RDSEED, for the generation of new random, the instructions SHA1 and SHA256 for cryptography. It also includes two new instructions called CLZERO and Coalescing PTE.

The first, CLZERO, is intended to clear a cache line and is more aimed at data centers and HPC crowds. This allows a thread to clear a cache line by automatically poisoning it in preparation for zero data structures. It also allows a level of respectability when the cache line is filled with the expected data, the CLZERO support will be determined by the CPUID.

Page Table Enty, or PTE coalescence, is the ability to combine small 4K page tables into 32K page tables, using a transparent software application. This is useful for reducing the number of TLB entries and queues, but requires certain criteria for the data to be used within the hop predicator that must be met.

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[nextpage title=”SENSEMI” ]

TECHNOLOGY SENSEM

AMD for AMD Ryzen processors has developed a completed architecture, called Zen. Within this new architecture, it has introduced a series of improvements or technologies in order to develop a platform that extends over time and allows users to enjoy a great power. AMD's idea was to break the mold and develop a processor that could compete with Intel's high-end and that could be perfected over time, either with the development of new processors based on this architecture or through drivers.

SenseMI is a set of five technologies intended to improve the performance of AMD processors. Each of these technologies have a very clear functionality, providing unprecedented power. For this development, three hundred expert engineers in different fields have worked together to bring this architecture to life exclusively and implement the five technologies that will be the pillars on which the AMD Ryzen processors will be built.

SenseMI Pure Power

Given the problems of previous families of processors with high consumption and high temperatures, AMD has taken action on the matter and has developed a system that avoids these problems efficiently and without affecting a drop in power. Within the processors a series of sensors have been included, whose purpose is to control and monitor the temperature, the working frequency of the processor and the voltage. These will be controlled and managed by a central control unit that will be in charge of managing consumption in real time.

This is possible thanks to Infinity Fabric technology. This system allows a generalized control of the parameters mentioned by means of the Infinity System Management Unit, which allows the processor to adjust consumption without losing power. It has been described by AMD as a fabric, therefore, it is possible that it is distributed throughout the processor, creating a network of several elements working together through a general control system.

All this can be summarized in that the Pure Power structure generates a lower and optimized DVFS curve for a silicon chip with respect to the generic DVFS curve, with which less energy will be consumed in several or all processes, depending on the power we need.

SenseMI Precision Boost

For many years, processors have implemented a feature called Boost, which is a kind of overclocking, which allows the processor to increase the frequency a bit for better performance. This function is completely automatic. The other part of this technology is the reduction of consumption when the processor is not under load, reducing its frequency and thus reducing overall consumption. The novelty of AMD is based on the optimized control of this system based on Pure Power, which makes the DVFS curve remain stable even with the frequency rise, since it does so at 25MHz steps.

Precision Boost is based on Pure Power and specifically on Infinity Fabric, allowing the frequency to scale according to consumption, so they both go hand in hand, optimizing both parameters. This is achieved by working in steps of 25MHz and not going from the base frequency to the maximum of Boost mode, without this being really necessary.

The current system used by AMD and Intel is based on multiplier adjustment. The Bus Speed ​​frequency is normally 100MHz and what is usually modified is the multiplier in these cases, AMD's solution is to scale this frequency and also adjust it with the multiplier, so that it is a more regular increase. AMD has lowered the minimum Bus Speed ​​frequency to 25MHz and increased the multiplier to x136, which would give 3.4GHz.

What the current processors did was keep the Bus Speed ​​stable and depend on the multiplier, increasing it in steps of x0.5 automatically. This causes excessive consumption and a hit in the frequency, which generates a consumption peak. AMD's proposal is to adjust it and increase both parameters in a scalable way, to avoid absurd consumption peaks and make the setting much cleaner. The user should not touch anything, in fact, nor will he notice anything, because it is something that the processor does on its own and automatically.

SenseMI Extended Frequency Range

One of the most interesting parameters of these processors is Extended Frequency Range, better known as XFR. This technology will not be available in all processors, but it is a very interesting solution that gives us an extra power that depends on the cooling system we are using. The processors right now have two frequencies, the base and the Boost and if you want more power, you must do overclocking yourself. Most processors still have an important window to improve performance when a good heatsink is installed, therefore we are wasting power and cooling capacity.

XFR wants to end this. The idea is to offer a stable way to scale the power, with a Boost mode and if the cooling system allows it, increase the frequency without putting the processor at risk at any time, therefore we do not underuse the processor's potential. with the cooler used. AMD has made it clear that the limit is around 60ºC and it is the cooler's mission to dissipate heat efficiently and quickly, so that the processor can offer almost unlimited power.

AMD has made it clear that this technology is automatic and that the user does not have to do anything at all, but it is possible that they implement some time of activation control system of the same through BIOS or perhaps it can be controlled from the AMD Ryzen Master Overclocking software, which we will talk about later. XFR allows users not to have to acquire knowledge of overclocking if they do not want or be afraid of touching something and having the processor break, although of course, we recommend learning a little, which never hurts, in addition, the software developed by AMD is quite intuitive and easy to use.

SenseMI Neural Net Prediction & Smart Prefetch

New generations of processors are developed in order to implement improvements and improve prediction to avoid performance loss and improve efficiency. One of the problems of the processors is the latency within each core, which is generated by the decoding of the instructions, generating a queue, in the movement between the different caches and the main memory in the movement and management of the chains of data. AMD introduces a prediction system called Neural Net Prediction to Ryzen to prioritize instructions.

AMD describes this technology as "a true artificial network within each Zen processor that builds a model of decisions based on the execution of software." This is explained in two ways, the first is that a real physical modeling of the workflow is generated in the instructions, identifying the critical paths and speeding them up, or the statistical analysis of what comes through the engine and trying to work during idle time. that could speed up future instructions.

Today's processors already have special instructions for repetitive work, identifying access to elements of a memory array and can pull data before it is ready, when needed. This system runs the risk of performing unnecessary tasks and in some cases the loss of time and work in unnecessary processes and generating jobs that become obsolete or useless.

According to AMD, what they have implemented in Zen is a system that allows the learning of algorithm models for instruction prediction and prefetch, which can be very interesting, as long as there is a good balance between prefetch and work. prediction as needed. This also makes it possible to take advantage of the increased bandwidth of the L3 cache in the cores, which helps to pre-capture key elements. The shared L3 cache generates a good system to contain the data that is already in use and vacate space to be used in later works.

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[next page title=”XFR” ]

EXTENDED FREQUENCY RANGE OR XFR

For some time now, there has been a lot of emphasis on Extended Frequency Range technology. AMD proposed this technology as an automatic overclocking system that depends directly on the heatsink, or what is the same, the more dissipation power it has, the more the processor frequency can increase. The theory was this, but now we know that it is not like that, at least for now.

The latest data from AMD says that the Ryzen 7 1800X and the Ryzen 7 1700X, can increase their frequency 100MHz, above the Boost mode, while for the Ryzen 7 1700, which in principle should not support this technology, if it will have a XFR, but 25MHz, in this case. This technology that we all wanted to know, we thought it would be a stable increase in the processor frequency, but a table shows something quite strange.

Processor frequencies are usually quite stable. We have the base frequency, which is the one that the processor will work at when it starts to have a load and the Boost mode, a frequency that is activated automatically when the load on the processor exceeds a certain threshold. Current processors also have a sleep frequency, which is activated to save power consumption and which is below the base frequency. Now, we also have the XFR, a frequency increase over the Boost mode.

We see in the graph how the XFR mode has been highlighted in a circle. It stands out that they are instantaneous frequency peaks, which hardly last in time, they are fast peaks that go up and down. In principle this is not the best, because for it to be a quality overclocking, it should be kept stable, since these peaks are generated, above all, it is an overconsumption. So that we understand it, it is like when we go in the car, we put first and we give full throttle to get out strong, that produces a great consumption, more than if the exit is gradual and stable, which consumes less the car.

XFR is possibly in a very early stage of development and has not been optimized or is not working properly. Maybe the motherboards need a future BIOS update for this technology to work well or it is a technology that is not optimized and finished and is seen in future processors with Zen architecture, we do not know, but the normal thing, at the very least, would be that the frequency remained stable over time and did not give these peaks.

[/nextpage] [nextpage title=”CHIPSET” ]

CHIPSET

The main features of the AMD Ryzen processors will directly support PCIe 3.0 x16 connectivity or two PCIe 3.0 x8 lanes. Regarding the connectivity of PCIe 2.0 lines, AMD Ryzen processors have two support for SATA 3 and one x2 NVMe, two SATA 3 ports and one PCIe x2 port or one x4 NVMe port. For USB connectivity, this motherboard supports up to four USB 3.1 Gen1 ports. The AMD Ryzen processors, we know that they will support DDR4 RAM, with a Dual Channel memory system.

X370 chipset

AMD Ryzen also requires new chipsets and the most powerful will be the X370 chipset, which has been considered by AMD as a chipset for the enthusiast segment. The main characteristic of this chipset is to offer support for overclocking, since all AMD Ryzen processors allow the modification of the multiplier, as we well know. The X370 is currently the only AMD Ryzen chipset that supports NVIDIA SLI and AMD CrossFireX configurations.

The X370 offers support for expansion of one PCIe Gen3 x16 lane or two PCIe Gen3 x8 lanes and also supports up to x8 PCIe Gen2 lanes. Regarding the connectivity ports, we have that this chipset supports two USB 3.1 Gen2 ports, ten USB 3.1 Gen1 ports and six USB 2.0 ports. It offers support for six SATA ports and one NVMe x2 port, although this can be modified by four SATA ports and one NVMe x4. It has support for two SATA Express ports.

B350 chipset

The lower version of the X370 chipset is the B350, which offers us slightly inferior characteristics, but which has also been designed for the entire range of AMD Ryzen processors. Like the X370 chipset, the B350 chipset offers support for overclocking, a feature that, as we have already said, all processors support. The chipset of the Performance range, such as this B350 chipset, offers support only for AMD CrossFireX and will not support NVIDIA SLI.

As with the X370 chipset, the B350 offers support for one PCIe Gen3 x16 lane and also offers support for a maximum of x6 PCIe Gen2 lanes. We move on to connectivity, where the B350 chipset offers support for two USB 3.1 Gen3 ports, six USB 3.1 Gen1 ports, and six USB 2.0 ports. The rest of the connectors of this chipset are divided into four SATA ports and one NVMe x2 or two SATA ports and one NVMe x4, in addition to offering support for two SATA Express ports.

[nextpage title=”COOLER” ]

COOLER

Ryzen processors will come with Wraith heatsinks, to properly cool the processor without having to invest extra money in a heatsink. The Ryzen 7 1800X and Ryzen 7 1700X, will initially carry the Wraith MAX, a cooler that supports a TDP between 95W, designed for these powerful processors, while the Ryzen 7 1700 will carry the Wraith SPIRE, a somewhat smaller heatsink that has a 65W dissipation power.

During the first moments, it was said that these two coolers would have an automatic function, which according to the color of the RGB LEDs, would indicate the temperature and state of charge of the processor, as well as if it was operating in XFR mode. All this has been left behind and they will be controlled manually, as far as lighting is concerned. In the end, they are powerful heatsinks with customizable lighting that can be synchronized with the lighting of the motherboard itself.

Wraith Spire will be the simplest, which is a mono block of dissipation fins with a 92mmm fan with two connectors, one with four PWM pins that is directly connected to the board and another cable that is connected to the USB 2.0 ports on board. (located at the bottom of the motherboard, normally). Wraith Max is the second of these coolers. It has a more robust design and has four heatpipes that pass through all the dissipation fins, enhanced cooling by a 92mm fan. This fan has two four-pin PWM connectors and a USB 2.0 connector that is connected to the on board ports. The USB connectors of both coolers are designed to synchronize the lighting or control it independently.

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[nextpage title=”RAM MEMORY” ]

RAM MEMORY

Ryzen is the first AMD processor to officially support DDR4 RAM. Intel for DDR4 developed the XMP profiles, which are simple profiles, controlled by BIOS and software, which allow information on characteristics and frequencies, among other settings for the RAM, to be stored in the RAM memory. AMD does not have anything similar, so everything will work the old way, in this case. But what interests us is to know what RAM will work and in what quantities and frequencies.

The DDR4 RAM in Ryzen will be Dual Channel, therefore the four modules will be divided into two primary and two secondary slots, so to speak. Direct communication between two modules will improve work, communication and performance. This is obvious, if you are going to build a computer, put two RAM memory modules and not just one, because you lose a lot of performance with such a configuration.

We are especially interested in the amount of DDR4 that it will support, which will be about 64GB, always depending on the model of the motherboard, chipset and other considerations, but that will be told by the manufacturer in the specifications. Regarding the frequencies, we see that these memories support 1866/2133/2400 / 2667MHz. Well, these are the frequencies that the processor will detect automatically without us having to tell it anything, if they were higher, then you have to enter the BIOS and touch some parameters. We must emphasize that it is very difficult to find DDR4 1866MHz memory on the market and normally, at least DDR4 is used working at 2133MHz.

It was also said that Ryzen in principle, would not support DRR4 ECC RAM, something that we have already discussed in a full article. Finally, Ryzen does support this type of RAM, although that Ryzen supports this type of RAM does not mean that the motherboard manufacturer supports it. Most motherboard manufacturers support ECC RAM on their motherboards, but working in non-ECC mode. Gigabyte, for example, admits that we install ECC memories on their boards, but they will always work as non-ECC. There is no problem, either, because normally we will not find this type of memory in stores, since the memories for gaming equipment are non-ECC, since ECC memories are destined for professional sectors, such as servers, data centers and others.

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[nextpage title=”TECHNICAL PROBLEMS” ]

TECHNICAL PROBLEMS

The last few days, since its launch, the AMD Ryzen processors in their entirety have been tested to the maximum, making them go through all kinds of tests. Everything suggests that AMD has run more than necessary in the launch of the processors, but the reality is that AMD was in a very uncomfortable situation and could not wait much longer to launch processors, something very important for AMD was to launch them this same year, with plenty of time for the Ryzen processors to make a significant gap before the arrival of the Intel Cannon Lake.

One of the first problems to be detected was the BIOS. There is a problem in them and it is that apparently they are not functional in the first motherboards and a major update of this is required. Some manufacturers already have updates that allow the DDR4 RAM to work at its factory frequencies and not below these frequencies, in addition, to offer support for AMD Memory Profile or AMP, which is the alternative to Intel XMP. Updating the BIOS should solve this problem.

Perhaps one of the most critical points is the cache memory latency. The latency of this memory has been found to be around 30ms higher than that of Intel processors and even that of the AMD Excavator. This would be because four cores share the L3 cache and they would not be able to do an optimal management. Apparently this is given by the CCX structure and it is possible that in this first batch of processors it does not work correctly. This affects the performance of the processor, since it forces to jump to DDR4 RAM due to cache performance problems.

Windows 10 is another of the conflict factors. It appears that Microsoft's operating system is not ready for these processors and has a major flaw. The operating system does not distinguish between the eight physical cores and the sixteen logical cores (SMT), therefore, it takes them all as physical cores. It doesn't seem like a problem, but SMTs are 20-30% efficient over physical cores and take care of secondary tasks. Loading these processors with primary tasks that require fast computation means that you have to wait for the task to complete, thereby wasting performance and processing time.

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[nextpage title=”GAMING” ]

GAMING

Expectations for Ryzen were very high, in every way. We have to think that AMD introduces processors with the Zen architecture, a new architecture that has been developed at full speed, since AMD urgently needed to put processors on the market. This causes the processors to not be at the level they should be and they have caused problems, well, rather, they have shown a lower than expected gaming performance.

It is a reality that in some games it is slightly below Intel processors and that in others it is quite below. The reality is that these processors have eight cores and there are only three or four games that are capable of running loading on more than four cores, therefore the number of cores in gaming is irrelevant. What happens is that a detail is being overlooked. AMD Ryzen processors are NOT intended for gaming.

We'll see. The Ryzen processors are giving a lot of cane in synthetic benchmarks where the number of cores does count and they are passing over the Intel processors. If we are going to render and do tasks that require power, at the core level and we are also going to play, the solution is clear, we are going to buy an AMD Ryzen upside down. Really buying an AMD Ryzen 7 to play is complete nonsense, because AMD Ryzen 7 processors, whatever we get, are not designed for gaming, for gaming they will be the Ryzen 5 and Ryzen 3, cheaper solutions.

Analyzing the processor under Windows 10, in addition, in tests we have realized that by changing the power mode of the operating system, we managed to improve the performance of these processors by 10-15%. Windows 10 is installed in balanced mode, which is designed so that at times of low load or no load, the voltage and frequency are reduced, therefore consumption drops sharply. Windows 10 lets us choose the 'High Power Performance' mode, which allows us to improve performance by 10-15%.

It seems crazy, but what this mode allows is to have a stable voltage on the processor, therefore the frequency will not drop at any time from the basic frequency of the processor. It is not silly, because the balanced mode in moments of low load can throw the consumption and the frequency and at a certain moment raise the load, for example in a game that loads a video of several minutes, the processor receives almost no load and it would lower voltage and frequency, the problem is that it must recover quickly and this is done in a scalar way to avoid strong blows and damage the processor. With the High Performance mode, we are always at the base frequency.

Logically, with this change we have a higher consumption, but we can change the mode when we are going to navigate and watch videos or simply, if we leave the equipment plugged in and go wherever and then, when we go to play, we activate the Alto mode again Performance and thus we will have a better performance.

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[nextpage title=”BENCHMARK” ]

BENCHMARK

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[nextpage title=”CONCLUSION” ]

CONCLUSION

The AMD Ryzen 7 1700 processor is undoubtedly a huge processor, although we have encountered problems and failures derived from the premature release of these processors to the market. The motherboard manufacturers highlight the problems of the BIOS that is about to end and that we will have to update as the updates arrive. We have updated it and we have noticed an interesting improvement. It must be remembered that it is not a processor that is not designed for gaming, but for tasks that require more load and weight.

This processor, like its older brothers, is designed for heavy tasks where a high-performance processor with many cores and processing threads is important, as in the case of photo or video editing, where the greater the number of cores, best. In gaming they do not behave as they should and AMD is already working on solving this setback and they will achieve it and these processors will beat the Intel processors in performance, because in price they already win.

We recommend the purchase for those who want to work in photo and video editing, streaming and gaming, without a doubt, since the performance 'problems' are irrelevant, since the difference between 100FPS and 120FPS is minimal and the price is really good. If we are looking for a processor for gaming, perhaps we should wait for the next Ryzen 5, which will be designed for gaming. The Ryzen 7 are a great option, of course.

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