AMD EPYC Rome will be based on Zen 2 architecture of 7nm lithography

We have already seen the first data of the 2nm lithography Zen 7 architecture that will be used in the next AMD EPYC.

We continue with the AMD New Horizon presentation where the company has presented the AMD EPYC processors which are based on the Zen 2 architecture that uses 7nm lithography. These processors for servers and data centers have a completely new CPU design, in addition to very important changes at the microarchitectural level from Zen @ 14nm. Second generation EPYC is developed to increase performance based on frequency and thus offer higher performance per watt.

Introduced AMD EPYC based on Zen 2 architecture that uses 7nm lithography.

As one would not expect otherwise, going from 14nm to 7nm means doubling the density of transistors in the same size of silicon at the same time that power consumption is reduced to 50% when they operate at the same frequency and if the frequency increases significantly the difference drops to 25%. This does not take into account other changes that will be integrated into the new Zen 2 design.

This new architecture offers an execution channel that has been completely redesigned, with an improved branched predictor, an improved instruction cache, instruction pre-lookup has been improved and a larger operations cache system, which will allow to increase the IPC of this architecture and frequencies, of course.

The new architecture offers twice the floating point performance of the original version of Zen, increasing the floating point computing power of 256 bits, which is a significant improvement for the company. AVX instructions are supported, something that to date only Intel Xeons did. AMD has also promised to mitigate Specter as much as possible in addition to developing a second-generation Infinity Fabric system that corrects some of the bottleneck issues.

Unfortunately, AMD has not provided performance data for the Zen 2 architecture, but the data provided can provide significant performance improvements, as well as higher work frequencies and a notable performance increase per clock cycle under certain workloads.

Zen 2 includes many changes thinking about EPY (and Ryzen, of course). Apparently it will have eight channels for RAM memory, just like the current EPYC. The I / O cores and the CPU are separated by dies, something that allows the I / O silicon to be developed at 14nm leaving only 7nm for the CPU cores.

AMD in the presentation has shown two 'chiplets' on the sides of the 14nm I / O, without specifying how many of these 'chiplets' Zen 2 will support the EPYC or how many cores will be integrated into the CPU. The design of the CPU is revolutionized in a notorious way allowing to address the memory problems that are denoted in the current Threadripper and EPYC.

We see that the 14nm I / O DIE at the top and bottom has four boxes with the infinity symbol, which would mean that each of them is connected to a CCX module. If each 'chiplet' has 2 CCX and each CCX has 4 cores and we see a total of 8 'Infinity Fabric' connectors, this would indicate that the EPYC will reach up to 64 cores (we multiply the 2 CCX by 4 cores by CCX and the result by the 8 'Infinity Fabric' connectors) without major problems, something that was already planned