It is always interesting to see how the different processor and graphics silicon are internally structured. VLSI engineer Fritzchens Fritz specializing in high resolution EM photography has published the silicon die for Renoir APUs. In addition to posting the images, he has added annotations for the different segments of these silicones, which is really interesting.
The diagram shows us how the CPU is the predominant part, while the iGPU occupies very little space. The processor space is increased with respect to the Picasso due to the duplication of cores distributed in CCX. The Renoir CCXs are smaller than the Zen2 CCDs available for the Matisse (Ryzen 3000) and Rome (EPYC 3000) MCMs.
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Images of the silicon-level layout of AMD Renoir APUs
The new Renoir will have two CCX modules, with 4MB of L3 cache for each CCX module, disintegrating the memory. This allows the CCDs in each CCX set to have their own cache and speed up performance.
We move on to the iGPU, whose limit under the Vega architecture is 8CU, which is 512 Stream Processors. So Renoir APUs have the same limitations as previous APU families in graphics power. AMD would have tried to compensate for this deficiency by increasing the frequencies by 40% over the Picasso (APU Ryzen 3000G).
Something that draws a lot of attention is the implementation of a PCI-Express physical layer. You can see 20 PCI Express lanes of 4 lines each and also two lanes of two SATA @ 6Gbps ports each.
Renoir will thus have 16 lanes for PCI-Express graphics, four lanes for the chipset and another four lanes dedicated to the M.2 NVMe port. For Renoir laptops it will be limited to 8 lines for a dedicated graphics card. Note that Picasso and Raven Ridge limit to 8 PCI-Express 3.0 lanes for dedicated graphics.
Source: TPU
