Intel CXL, an interconnect system that reduces latency and improves system performance

Robert Sole 9 April 2019

2 1.790 2 reading minutes

Introduced by Intel, CXL technology, a PCIe communication system that reduces latency and improves hardware performance.

The arrival of the new Intel graphics cards is revolutionizing the market in a notorious way. Little is known about the architecture of these graphics cards, their power or the memories they will incorporate. Although the company is giving data about it, like last night at Intel Interconnect Day 2019. The company explained the Compute Express Link (CXL) protocol within the conference. This protocol is used to interconnect the new graphics cards of the company.

Intel gives data on the new CXL technology

This new protocol is a system that relies on I / O, memory, and interface consistency. It seeks to offer a high performance interconnection with a high transfer speed. This technology is based on the PCI Express system, taking advantage of the physical and electrical interface PCIe 5.0 (CXL 1.0), for all three highlights.

CXL is based on the PCIe 5.0 interface for interconnection of computer acceleration systems, such as graphics. The company emphasizes that computing in the future will require systems with very low latency. It also highlights that coherent memory systems will be needed instead of being isolated by PCIe. Initially PCIe Gen5 will offer a 32Gbps bus, which would fall short in no time. So the company is already working on PCIe Gen6 which will offer better bandwidth.

Three protocols based on CXL will be considered:

io: data input and output via PCIe
Cache - Gives compute accelerators direct access to the processor cache using 64-byte cache lines
memory: allows the processor to access the device and access its memory

Depending on the protocol used by the processor and the interconnected device, the requests will vary between questions and answers, being a transparent process. This offers direct access to the cache and HBM memories with really low latency.

CXL: asymmetric and open protocol

QPI or UPI cache and storage access systems are symmetric. CXL leaves that system behind to add major changes to upcoming processors. This new CXL will be completely asymmetric and open, allowing multiple devices to cross information on a single platform.

For scalable server systems, this technology is interesting, since Intel would not have to use UPI in its processors. They would go on to use CCIX and the adoption of CXL, offering any device access to memory without going through the processor. This allows to reduce latency significantly.

This for Intel Xe graphics is a great solution, as it allows memories to access information quickly and without being limited by processors. But it is that this new interconnection system offers a global system of hardware acceleration without performance drops. A technology, which on the other hand would not arrive until 2021, since currently PCIe Gen4 is still arriving and this protocol would not be good enough.