The AMD EPYC Rome will have a new memory matrix to correct bottlenecks

New design for the memory matrix of the AMD EPYC Rome that will solve the bottlenecks that are generated today.

Data Centers are a very important market and offering quality solutions is a priority for AMD, who is clear that EPYC is a very interesting solution for this market. The new EPYCs would make use of up to four 8-core Zeppelin arrays. Each of these arrays will have its own integrated north bridge, which allows controlling the dual channel DDR4 RAM and will also have a complex 3.0-lane PCIe Gen 32 root system. Clearly, the problem of memories that generated bottlenecks will be solved and that will not be present in Rome.

AMD EPYC Rome will have a new design for memory that solves the bottleneck.

Without going any further, the Threadripper WX have serious bottleneck problems, especially in video encoding applications that make use of a large amount of memory, generating significant performance drops in those matrices that do not have direct access to the I / O system. S due to bandwidth. Correcting this problem has been possible thanks to a processor design with a disabled Northbridge that was implemented in the second generation EPYC Rome.

The next generation MCMs will have a completely centralized design at the point of the system controller that will be surrounded by the DIEs and that everyone will be able to access the interposer, something similar to what is used in the Vega 10 and in the Fiji.

An interposer is a special silicon matrix that facilitates interconnection at the microscopic level with a high density between MCM matrices. It differs from the current EPYC in that this new interface is large, somewhat similar to the one used by Intel.

The interface has a complex PCIe Gen 4.0 x96 root system that would allow managing up to six graphics with a x16 bandwidth or up to twelve x8 type. Said Matrix will integrate a Southbridge named Server Controller Hub for greater bandwidth in the I / O interfaces.

Source: TPU