Samsung Abandons Development of 3nm FinFET Chip Manufacturing Process

Important announcement from Samsung, who has announced that it is leaving aside the development of the 3nm FinFET, moving to another manufacturing process, which should be simpler and eliminate the limitations of the FinFET model.

Silicon has reached a critical point, when it comes to miniaturization of transistors. Intel's problems with 10nm lithography appear to be unique, but TSMC has already announced that 5nm could be delayed much longer than expected, due to running into problems. During the Samsung Foundry Forum, the South Korean company itself, which is the largest chip manufacturer in the world, at this time, has announced that it is abandoning the development of chips in 3nm FinFET.

Roadmap change on Samsung

The announcement of the company has surprised, which has modified its Roadmap, focusing on developing energy efficient chips, thinking about all types of industries. Charlie Bae, Executive Vice President and Director of Sales and Marketing at Samsung, has said that 'the trend is towards a more intelligent and connected world, which makes the industry demand more from silicon suppliers'

The company is working on the Lower Power Plus process at 7nm based on EUV lithography, a manufacturing process that will begin to enter mass production during the second half of this year and is expected to be expanded during the first half of 2019. The next process will be Low Power Early 5nm, which will offer an energy improvement over 7nm. These processes will be based on the FinFET design, just like the 4nm process.

It will be at 3nm, when the FinFET will be abandoned and the 3nm Gate-All-Around Early / Plus process will take place. This process will be based on a new type of transistor that should solve the scaling problems that the FinFET process has and that is causing so many headaches in the industry. This jump should be made in 2022, but it may be delayed by at least two years.

We must emphasize that the size limit of a transistor in silicon is established at 1nm, so we are approaching this barrier. The closer we get to this size, the more difficult it is to make the leap towards greater miniaturization, therefore, it is possible that advances will cost more and more and there are delays while waiting for a material that can replace silicon.

Source: tech spot