TSMC shows how its 5nm lithography goes

The lithography race has accelerated and is costing some more than others. Intel has trouble making the jump to 10nm because its production efficiency would be low. Samsung seems to be going at a good pace, but it is behind TSMC, who is going full blast. The Taiwanese company has spoken about 5nm during the IEEE congress.
TSMC, the Taiwanese foundry that has managed to overtake Samsung, is expected to launch 5nm in 2020. By the second quarter of next year they will be able to produce processors under this new lithography. Initially it would be HiSilicon, a subsidiary of Huawei and Apple who will receive the first chips under this lithograph.
No products found.
TSMC takes its chest out of its 5nm lithography
During the presentation they talked about the level of productivity of their lithographic process. This is nothing more than the number of functional processors generated during its manufacture. Currently TSMC has an efficiency of 80%, which indicates that the level of production of processors per wafer is doing very well. That some are defective is normal and always happens.
The foundry is currently working on improving the production efficiency of the processors. We must bear in mind that the greater the number of valid processors per wafer, the more the cost of the final processor is reduced. Intel's problem with 10nm would be precisely that the error rate per wafer is high.

They have also highlighted that this process for smartphone chips, for example, is very good, but for large processors it does not go so well. For manufacturing large 5nm chips, such as AMD processors, the hit rate is 32%. This forces TSMC to redouble its efforts to reduce the error rate. They have time, as AMD has no plans to launch 2021nm processors until 5.
This 5nm lithographic process has been developed to generate at least ten layers using extreme ultraviolet light (UVE). It reduces wafer production time and improves power, as well as the area and consumption of the chips. TSCM highlighting a reduction in area of up to 45%, an improvement in power of 15% and a reduction in consumption of 30%.

Source: Anandtech



