The specialized medium Hardware.fr delves into the performance of the cache of AMD Ryzen processors and we see that there is a problem with the latencies of this memory.
AMD Ryzen processors are performing below expectations in certain applications and in gaming and the problem lies in one point: memory. The AMD Ryzen processors before they hit the market, it was commented that these processors had been developed with a large number of new technologies and instructions within their architecture to offer maximum performance in each of their cores. We have seen in practice how, it has not been possible for these processors to work as intended.
We still have to wait for the arrival of the Ryzen 5 and Ryzen 3 processors to know that the performance problems will be solved, but the improvement in the management of the latency of the L3 cache seems quite complicated. To see how the cache really performs, the specialized medium Hardware.fr, has worked to see how the cache performs and the differences with other processors using AIDA 64. The benchmarks seem to suggest some kind of problem in the use of the L3 cache.
We see in the comparison, how the Ryzen 7 1800X processor gives a latency of 98ms, while the i7 6900K and FX 8350 processors, give a result that is around 70ms, with which these new AMD processors have a higher latency in practically 30ms, which directly affects the performance of the processor, since the more latency, the longer it takes to load the instructions.
The L1 cache has also been tested, it is still in performance, as you can see ahead of Intel's, while the Ryzen's L2 seems to be slightly more powerful. The problem basically resides in the L3, which is the furthest from Intel's, with almost three times more latency than in the i7 6900K.
The problem is magnified when the load increases. The Intel processor has a 1Kb L32 cache, which offers higher performance in workloads and when the instruction packets exceed that size, it passes it to the L2 cache which is 256Kb. For uploads greater than 256Kb and less than 16MB, they are passed to the 3Mb L20 cache on the Intel processor. If the size of the instruction exceeds 16Mb, it already passes it directly to the RAM, which has a latency of approximately 70ms.
The thing changes a lot in AMD Ryzen processors, since the latencies are quite high. The L1 cache is 32Kb and the L2 cache is 512Kb. The problem lies in the jump to the L3 cache which is 16Mb, which is where it behaves differently. The latency in 4Mb packets is more or less stable, but when we pass that ceiling things start to skyrocket in terms of latency. This seems to be a problem with the modularity of AMD Ryzen processors, with their CCX structure (it consists of 4 cores and 8MB of L3 cache), which only allows access to up to 8Mb of L3 cache at any time.
We can explain this through the design of the Ryzen processors, which affect access times, depending on the volume of the package that must go through the L3, due to the CCX design. This means that the processor is 'divided' into two CCX parts and therefore each of the 'divisions' would only have access to 8MB of L3 cache. Even if we focus the load on the cores closest to the CCX division, to make use of the entire cache, we would be limited by the CCX bandwidth, which is 22GB / s, which is much lower than 175GB / s L3 cache and also less than RAM bandwidth.
Of course, AMD Ryzen processors are good, but we see that they hit the market without being polished and with certain problems. The reality is that AMD had no alternatives, no options, it had to launch a processor now, whether it was 100% or 50% developed, they didn't care, but they couldn't afford more time on the bench seeing how Intel was gaining more and more ground. . This generation of processors gives us good performance and excellent features, but surely Zen 2 and Zen 3 will solve these problems and will be complete and powerful processors, since the current Ryzen, to put it in some way, are a beta phase, the which offers quite an interesting performance.
Source: Hardware.fr



The concepts explained in this article do not conform to reality. The cache memory hierarchy is intended to predict the use of the next possible instructions and data. The performance of a cache memory hierarchy is not measured by the latency of levels l1, l2, l3 or how many there are, but by its hit rate. Levels L1 and L2 are decisive. In any case, the algorithm for predicting instructions and data and the size of the cache are what determine the success rate. Nothing assures you that with lower latency the processor will process more instructions….
What you say is true, the hit rate is essential.