Future of AMD: Chiplet, Stackable Memory and Renewed Interconnect Systems

During a conference AMD has revealed that its future goes through chiplets for everything, better connection buses and stackable memories.

This year will be key for the future of AMD, not so much in the segment of processors, but in the segment of graphics. Radeon is the graphics division of the company that is in a really bad time. It takes a revolution and abandon GCN at once, being a very bad design and above all, highly energy inefficient. For this the company has presented a new solution at the HDPC Oil and Gas Conference. Forrest Norrod has starred in a talk called: "Evolving Systems Design for HPC"

The fundamental chiplets for AMD

According to the conference, the company establishes that monolithic processors have their days numbered and that the solution is chiplets. But it is that AMD is clear that the chiplets for them are a reality, come on, that they will not turn back. They also refer to working in systems that go beyond Moore's Law, which had already become obsolete.

Although monolithic processors (all in a single silicon) have advantages, there is the problem of the size and number of transistors. This problem has taken several generations and it seems to be evolving at a good pace. But we have also seen how Intel is having problems with 10nm and the TSMC problems that it has had with 7nm, although they have been minor, have also caused delays. But it is also that in a maximum of 20 years we will reach transistors the size of an atom, a barrier that we do not know how to overcome.

So AMD has considered how to solve this problem and Lisa Su would have helped design or at least devise the MCMs. We are talking about Multi-Chip Architecture, also known by AMD as Chiplet. This allows easy scaling to large numbers of transistors and cores.

MCM as a solution to Moore's Law

Creating processors or chips for specific tasks should significantly improve aspects such as: smaller DIE sizes, lower costs, higher performance and greater scalability.

But this presents other challenges such as creating a new architecture interconnect system like CCIX or Caché Coherent Interconnection for Accelerators. Another solution is Gen-Z or Open Systems Interconnection for Semantic Access from Memory to Data and Devices. The problem with these systems is latency, as we have already seen in the first and second generation Infinity Fabric, which should improve a lot for the third generation of Zen2-based Ryzen processors.

"On-DIE 3D Stacked Memory" in processors and graphics

One highlight is memory innovation, where the company has discussed 3D On-DIE Stacked Memories. While this technology is still under development, a prototype could be seen in the next few years. This type of memory should compete with Intel Foveros, the solution being developed by AMD's competitor.

Regarding CCIX and Gen-Z there is still no data on their impact on processors and graphics, although of course, this is an informative presentation. But stacking layers in the same DIE is not a novelty since NAND Flash memories already have 96 layers, which allows to increase the capacity of SSDs and reduce their prices.

It is evident on the other hand that AMD is working on its own 3D technology for silicon, something that Intel has had for years. It would be a system similar to WoW from TSMC, a memory overlay system, from chips or directly from SoC. We'll see if CCIX and Gen-Z is capable of fighting Intel's CXL, Intel's stacking system.

EPYC ROME focuses directly on MI-Next

Supposedly in the middle of the year we will see EPYC ROME, the 64-core and 128-thread processors based on 7nm lithography. These Zen 2-based processors should be an excellent solution for the server and data center market. Some processors that would increase instructions per cycle, support for PCIe 4.0 and a chiplet design. For 2020 we will see EPYC MILAN with Zen 3 architecture and of which nothing is known.

Cray, according to AMD has said, would be using EPYC ROME processors to develop NERSC-9, commercially named as Shasta. These processors will be accompanied by NVIDIA Tesla graphics on a server for supercomputing that will cost 146 million dollars.

Source: OC3D